As electrical/electronic appliances have been advanced with high performance, technology for attaching a greater number of packages onto a substrate having a limited size has been proposed and studied. However, since it is a rule to mount only one semiconductor chip in a package, there is limitation to obtain a desired capacity.
As a method of increasing a capacity of a memory chip, that is, as a method of achieving high integration, technology of installing a greater number of cells in a limited space has been generally known in the art. However, such a method requires high level technology such as a precise design rule and a lot of development time. Thus, as a method for easily achieving high integration, a stacking technique has been developed and the study for the sacking technique has been currently performed very actively.
To this end, an MCP (Multi Chip Package) technique has been recently utilized.
The MCP is a semiconductor product prepared in the form of one package by stacking several memory chips, so the MCP not only reduces the volume of the semiconductor product, but also increases the data storage capacity, so that the MCP is mainly used in portable electronic equipment such as a mobile phone.
In this case, since several tens of semiconductor chips are stacked to be stably operated while minimizing the thickness thereof, the high level technique is required from the design stage to the production stage.
FIG. 1 is a view showing a package system according to the related art.
Referring FIG. 1, the package system includes a semiconductor package substrate 10, a dummy die 20, and a memory chip 30.
The semiconductor package substrate 10 includes at least one circuit pattern formed on an insulating substrate. A protective layer for protecting the circuit pattern is formed on the circuit pattern (uppermost layer of the semiconductor package substrate 10).
The memory chip 30 may be a nand flash memory chip.
The dummy die 20 is formed between the substrate 10 and the memory chip 30.
The dummy die 20 provides an attaching space for allowing the memory chip 30 to be attached onto the semiconductor substrate 10 while spacing the semiconductor substrate 10 from the memory chip 30.
However, since the package system described above must form the dummy die 20 between the semiconductor substrate 10 and the memory chip 30 for stacking the memory chip 30, an additional process is required in addition to a process for manufacturing the semiconductor substrate 10, so that productivity of a manufacturer is reduced.
Further, since the dummy die 20 is formed of an expensive silicon material, a cost of the entire package system is increased.
In addition, since the silicon dummy die 20 has a predetermined thickness, the entire thickness of the package system is increased.